High speed receivers (Rx) must typically be able to account for jitter. Jitter may be present in data (e.g., through channel loss and/or intersymbol interference (ISI)) the Rx receives and may also be induced by components within the Rx itself. Such jitter inducing Rx components may include a phase-locked loop (PLL), a clock-tree or clock hub, a phase interpolator (PI), clock-and-data recovery (CDR) logic components, and the like. In typical eye-tracking architecture Rx clock jitter (e.g., arising from a PLL, clock distribution, and/or PI) is a significant portion of the Rx's jitter eye budget. (Note: An “eye” diagram provides an intuitive view of jitter and is a composite view of multiple bit periods of a captured waveform superimposed upon each other.)
Conventional eye-tracking architecture has relatively low power requirements and relatively decent jitter tolerance. An example of such architecture is included in FIG. 1, where four-phases of clock signals (PH1, PH2, PH3, PH4) are generated from PLL 105 and sent to different lanes via clock tree/hub 110. The phase of these clocks is then adjusted via PI 115 before logic 100 samples incoming data (DP, DN) via samplers 116, 117, 118, 119. The phases of the output from PI 115 are controlled via CDR 120. CDR 120 generates the advancement or retardation of the phases of E1, D1, E2, D2 by looking at both edge and data output coming from samplers (E1, D1, E2, D2) and then modifying the output from CDR 120 accordingly to correct phase/timing issues via PI 115. Based on this closed feedback loop (which includes CDR 120), PI 115 output clocks track the center and edge of incoming data DP, DN to compensate for jitter.